1. Field of the Invention
The invention relates to the manufacture of highly dense integrated circuits and more particularly to a very manufacturable method for making sub-micron MOS (Metal Oxide Semiconductor) devices.
2. Description of the Related Art
In the manufacture of highly dense integrated circuits using Metal Oxide Semiconductor Field Effect Transistors (MOSFET) technology, as device dimensions decrease, there has been a need to create shallower source/drain regions. However, corresponding high doping concentrations lead to an increase in the electric field in the device channel in the region adjacent to the drain. This high electric field causes electrons in the device channel to gain energy and be injected into the gate oxide. This phenomenon is known as the "hot carrier" problem, which leads to long-term device degradation and reduced reliability.
A second problem with highly dense MOS devices, particularly P-channel MOS (PMOS) structures with sub-micron feature sizes, is the so-called "short channel effect". Since the ions, typically boron B11 or boron fluoride BF.sub.2, that are used to form the source and drain regions have a higher diffusion coefficient than the arsenic or phosphorus ions used to form the N-channel MOS (NMOS) source/drain regions, the effective channel length of the PMOS device will be less than that of an NMOS device formed on the same substrate.
Workers in the art are familiar with these problems and have attempted to overcome them. A method to reduce the high electric field at the drain region is to provide a more gradual, or graded, change in the doping concentration at the drain/channel interface. One means of accomplishing this is with a lightly doped drain (LDD), as described in "VLSI TECHNOLOGY", by S. M. Sze, published by McGraw-Hill International-Singapore, 1988, pages 482-483. As shown in FIG. 1, a substrate 10 is implanted with a heavy implant to create regions 12, and an implant with lighter doping concentration to form regions 14. Also shown are gate 25 which is separated from the device channel by gate oxide 24. A smaller electric field results at the drain/channel interface than would exist in a device in which a single heavy implant was performed, due to a reduction in the difference in dopant concentrations between the channel and the drain region adjacent to it. This may also be accomplished by a LATID (Large Angle Tilt Implanted Drain), in which, before spacer formation, a long N- region is formed by ion implanting while tilting the wafer with respect to the implant. A smaller electric field results at the drain/channel interface than in the LDD structure. Also, because the maximum point of the lateral electric field at the drain edge is not at the main path of channel current, the degradation caused by the hot-carrier effect is reduced.
The short-channel effect may also be overcome using a Halo structure. After poly gate formation, source/drain extensions are formed which are self-aligned to the poly gate edge and are composed of a lightly doped shallow region (LDD) and a deeper oppositely-doped pocket or "halo". The Halo structure can be formed by a LATID or double-implant LDD technique. This structure serves to increase the punchthrough voltage of the device and decrease the short channel threshold voltage falloff, because the influence of the drain electric field is confined by the oppositely-doped Halo. This structure also provides increased device performance because it allows use of a low impurity concentration in the substrate and in the channel region, to attain high carrier velocity.
An anti-punchthrough implantation is needed in the formation of submicron MOS devices because the well concentration is too light to prevent device punchthrough and the short-channel effect.
Therefore, in the formation of a sub-micron integrated circuit with both PMOS and NMOS devices, there are two masking steps and two implantation steps for each of the anti-punchthrough implant, the LDD formation, and the source/drain formation.